1. Technical Field
The present invention generally relates to a method of manufacturing a non-volatile memory device. More particularly, the present invention generally relates to a method of manufacturing a dielectric layer in a non-volatile memory cell having a silicon oxide nitride oxide semiconductor (SONOS) structure.
A claim of priority is made to Korean Patent Application No. 2004-2136, filed Jan. 13, 2004, the disclosure of which is hereby incorporated.
2. Discussion of the Related Art
Generally, non-volatile memory devices are classified into a floating gate memory device and a metal nitride oxide semiconductor (MNOS) memory device. In the floating gate memory device, erasing is accomplished by transferring electrons from the floating gate; programming is accomplished by transferring electrons into the floating gate. In the MNOS memory device, charge or data is stored in the nitride trap layer.
The conventional MNOS memory device has a metal nitride oxide semiconductor (MNOS) structure or metal oxide nitride oxide semiconductor (MONOS) structure. If a gate is composed of a polysilicon layer instead of a metal, the memory device has a silicon oxide nitride oxide semiconductor (SONOS) structure.
FIG. 1 is a cross-sectional view illustrating a conventional dielectric layer having the SONOS structure.
As shown in FIG. 1, the conventional dielectric layer has an ONO structure in which, a first oxide layer 12, a nitride layer 14, and a second oxide layer 16 are laminated on a semiconductor substrate 10. First oxide layer 12 is a tunnel oxide layer, second oxide layer 16 is a blocking oxide layer, and nitride layer 14 is a charge storage layer.
A method of manufacturing the dielectric layer having the ONO structure is disclosed, for example, in U.S. Patent Application Publication No. 2003.
In the conventional non-volatile memory having the SONOS structure, when high voltage is applied to a gate, electrons tunnel through a substrate and then the electrons are stored in a trap layer.
During data programming, if the trap layer is at a low energy level, charges stored in the trap layer are easily lost, i.e., data is lost. On the other hand, if the trap layer is at high energy level, charges stored in the trap layer are difficult to remove, i.e., data cannot be easily erased. Further, data programming and erasing operations are influenced by a trap area at an interface between an oxide layer and a nitride layer, therefore, causes instability of the memory device. Also, data retention problem occurs when the charge storage layer contains hydrogen (H+). Therefore, developments have been actively pursued for SONOS devices with easier programming and erasing abilities, faster operational speeds at low voltage, and increase memory capacity.